NikhilChaubey

https://github.com/maciejjo/beaglebone-pru-dma https://elinux.org/BeagleBoard/GSoC/BeagleBone_PRU_DMA https://gist.github.com/maciejjo/58a0d0213712e67fba9d0061f6b5bead https://www.glennklockwood.com/embedded/beaglebone-pru.html  https://github.com/maciejjo/beaglebone-pru-dma https://elinux.org/BeagleBoard/GSoC/BeagleBone_PRU_DMA https://gist.github.com/maciejjo/58a0d0213712e67fba9d0061f6b5bead https://www.glennklockwood.com/embedded/beaglebone-pru.html Understand overlay: WL1835 ------------------------------------------------------------------------------------------- https://www.kernel.org/doc/Documentation/devicetree/bindings/net/ti%2Cwilink-st.txt https://wiki.st.com/stm32mpu/wiki/Dmaengine_overview mmc property: am335-sdhci to search driver sdhci-omap.c and understand how dma is used in it. EDMA registers TPCC (EDMA3CC) 0x4900_0000 0x490F_FFFF 1M BEDMA3 Channel Controller Registers TPTC0 (EDMA3TC0) 0x4980_0000 0x498F_FFFF 1MB EDMA3 Transfer Controller 0 Regist...

 uboot: https://blog.csdn.net/zhoudengqing/article/details/41345859 https://m2m-tele.com/blog/2021/10/24/u-boot-initialization-sequence/ U-boot has to reserve 3 regions in memory that stores: 1) u-boot itself, 2) uImage (compressed kernel), and 3) uncompressed kernel. These 3 regions must be carefully placed in u-boot to prevent conflict. However, the previous stage boot-loader, (BL2 or BL1) that brings u-boot into DRAM memory don't know u-boot's planing on these 3 regions. So it can only loads u-boot onto a lower address in DRAM memory and jump to it. Then, after u-boot execute some basic initialization and detect current PC is not in planed location, u-boot call relocate function that move u-boot to the planned location and jump to it. First stage executes on starting memory area. Than during relocation procedure U-boot copies itself to the end of RAM memory by address calculated on last steps of first stage and jumps to new address after that. Second stage executes on final ...

https://github.com/embear-engineering/u-boot/tree/elc-2024-from-hardware-to-linux https://github.com/nghiaphamsg/BBB-linux-device-driver https://blog.csdn.net/ZZZZZ1113/article/details/131142606?spm=1001.2101.3001.6650.2&utm_medium=distribute.pc_relevant.none-task-blog-2%7Edefault%7ECTRLIST%7ERate-2-131142606-blog-117647308.235%5Ev38%5Epc_relevant_sort_base3&depth_1-utm_source=distribute.pc_relevant.none-task-blog-2%7Edefault%7ECTRLIST%7ERate-2-131142606-blog-117647308.235%5Ev38%5Epc_relevant_sort_base3 https://blog.csdn.net/hexiaolong2009/article/details/102596772?spm=1001.2101.3001.6650.18&utm_medium=distribute.pc_relevant.none-task-blog-2%7Edefault%7EBlogCommendFromBaidu%7ERate-18-102596772-blog-102641233.235%5Ev38%5Epc_relevant_sort_base3&depth_1-utm_source=distribute.pc_relevant.none-task-blog-2%7Edefault%7EBlogCommendFromBaidu%7ERate-18-102596772-blog-102641233.235%5Ev38%5Epc_relevant_sort_base3 https://blog.csdn.net/dragon101788/article/details/99673427 https://s...

 https://www.cs.cmu.edu/~412/lectures/Virtio_2015-10-14.pdf https://player.slideplayer.com/5/1509596/ https://abelsu7.top/2019/09/02/virtio-in-kvm/ https://www.cnblogs.com/LoyenWang/p/14444344.html https://www.cnblogs.com/LoyenWang/ https://www.cnblogs.com/LoyenWang/p/13584020.html https://www.embedded.com/understanding-virtualization-facilities-in-the-armv8-processor-architecture/ https://auriga.com/blog/2018/armv8-virtualization/

 when an IRQ is raised, the kernel executes some assembler code in order to save  the current state and jumps to the arch-specific handler, handle_arch_irq. For ARM architectures, this handler is  set with the value of the handle_irq field in struct machine_desc of the platform in the setup_arch() function implemented in arch/arm/kernel/setup.c. The assignation is done as follows: Shared IRQ: https://stackoverflow.com/questions/14371513/for-a-shared-interrupt-line-how-do-i-find-which-interrupt-handler-to-use The kernel will sequentially invoke all the handlers for that particular shared line. Exactly. Say Dev1 and Dev2 shares the IRQ10. When an interrupt is generated for IRQ10, all ISRs registered with this line will be invoked one by one. In our scenario, say Dev2 was the one that generated the interrupt. If Dev1's ISR is registered first, than its ISR (i.e Dev1's ISR) only called first. In that ISR, the interrupt status register will be verified for interrupt. If no int...

 client driver write i2c calls to i2c-core. i2c-core calls goes to vendor specific i2c calls. device tree: i2c controller andd slaves i2c1: i2c@400a0000 {         /* ... master properties skipped ... */         clock-frequency = <100000>; //slave1         flash@50 {                 compatible = "atmel,24c256";                 reg = <0x50>;         }; //slave2         pca9532: gpio@60 {                 compatible = "nxp,pca9532";                 gpio-controller;                 #gpio-cells = <2>;                 reg = <0x60>;         }; }

 https://elinux.org/Tools_and_Debugging_Presentations https://elinux.org/Debugging_by_printing initcall_debug: https://elinux.org/Initcall_Debug https://stackoverflow.com/questions/37272109/how-to-get-details-of-all-modules-drivers-that-were-initialized-probed-durin/37283021#37283021 dynamic debug: https://www.linuxjournal.com/content/oops-debugging-kernel-panics-0